`timescale 1ns / 10ps
`define clock_period 20

module switch_2bit_tb;

	reg data1;
	reg data2;
	reg data3;
	reg data4;
	reg [1:0] switch_signal;
	
	wire cout;

	switch_2bit sw0(
		.Data1(data1),
		.Data2(data2),
		.Data3(data3),
		.Data4(data4),
		.Switch_signal(switch_signal),
		.Cout(cout)
	);
	
	initial begin
	
		data1 <= 1'b1;
		data2 <= 1'b0;
		data3 <= 1'b1;
		data4 <= 1'b0;
		switch_signal <= 2'b00;
		#(`clock_period)
		switch_signal <= 2'b01;
		#(`clock_period)
		switch_signal <= 2'b10;
		#(`clock_period)
		switch_signal <= 2'b11;
		#(`clock_period)
		
		$stop;
	
	end

endmodule
